Overview
- An innovative presentation of the theory of disjoint support decomposition, presenting novel results and algorithms, plus original and up-to-date techniques in formal verification
- Provides an overview of current verification techniques, and unveils the inner workings of symbolic simulation
- Focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them
- Addresses key topics in need of future research
- Includes supplementary material: sn.pub/extras
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Table of contents(7 chapters)
About this book
Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions.
In structuring this book, the author’s hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research.
Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field.
Highlights:
- A discussion of the leading hardware verification techniques, including simulation and formal verification solutions
- Important concepts related to the underlying models and algorithms employed in the field
- The latest innovations in the area of symbolic simulation, exploiting techniques such as parametric forms and decomposition properties of Booleanfunctions
- Providing insights into possible new developments in the hardware verification
Authors and Affiliations
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Advanced Computer Architecture Lab Department of EE & CS, The University of Michigan, Ann Arbor, USA
Valeria Bertacco
Bibliographic Information
Book Title: Scalable Hardware Verification with Symbolic Simulation
Authors: Valeria Bertacco
DOI: https://doi.org/10.1007/0-387-29906-8
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2006
Hardcover ISBN: 978-0-387-24411-2Published: 21 December 2005
Softcover ISBN: 978-1-4419-3739-1Published: 29 October 2010
eBook ISBN: 978-0-387-29906-8Published: 14 May 2006
Edition Number: 1
Number of Pages: XX, 180
Number of Illustrations: 40 b/w illustrations
Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design, Computer Hardware, Electrical Engineering