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Functional Verification of Programmable Embedded Architectures

A Top-Down Approach

  • Book
  • © 2005

Overview

Authors:
  1. Prabhat Mishra

    1. Department of Computer and Information Science and Engineering, University of Florida, USA

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  2. Nikil D. Dutt

    1. Center for Embedded Computer Systems Donald Bren School of Information and Computer Sciences, University of California, Irvine, USA

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    You can also search for this author in PubMed   Google Scholar

  • Includes the latest studies/statistics on both verification complexity and design failures
  • Provides a complete view of the existing specification languages for programmable architectures
  • Demonstrates the development of functional fault models and coverage estimation techniques

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Table of contents (7 chapters)

  1. Front Matter

    Pages i-xix
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  2. Introduction to Functional Verification

    1. Introduction

      Pages 3-12

  3. Architecture Specification

    1. Architecture Specification

      Pages 15-28

    2. Validation of Specification

      Pages 29-62

  4. Top-Down Validation

    1. Executable Model Generation

      Pages 65-82

    2. Design Validation

      Pages 83-93

    3. Functional Test Generation

      Pages 95-117

  5. Future Directions

    1. Conclusions

      Pages 121-123

  6. Back Matter

    Pages 125-180
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Keywords

About this book

It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems.

Authors and Affiliations

  • Department of Computer and Information Science and Engineering, University of Florida, USA

    Prabhat Mishra

  • Center for Embedded Computer Systems Donald Bren School of Information and Computer Sciences, University of California, Irvine, USA

    Nikil D. Dutt

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